Contents
xxvi ADSP-21368 SHARC Processor Hardware Reference
Input Data Port Control Register 1 (IDP_CTL1) .................. A-68
Input Data Port FIFO Register (IDP_FIFO) .......................... A-69
Input Data Port DMA Control Registers ............................... A-70
IDP_DMA_Ix .................................................................. A-70
IDP_DMA_Mx ................................................................ A-71
IDP_DMA_Cx ................................................................. A-71
Input Data Port Ping-Pong DMA Registers ............................ A-72
IDP Ping-Pong Index Registers (IDP_DMA_IxA) ............. A-72
IDP Ping-Pong Count Registers (IDP_DMA_PCx) ........... A-73
Parallel Data Acquisition Port Control Register
(IDP_PP_CTL) ................................................................. A-74
Pulse Width Modulation Registers .............................................. A-78
PWM Global Control Register (PWMGCTL) ....................... A-78
PWM Global Status Register (PWMGSTAT) ......................... A-79
PWM Control Register (PWMCTLx) .................................... A-80
PWM Status Registers (PWMSTATx) .................................... A-81
PWM Period Registers (PWMPERIODx) .............................. A-81
PWM Output Disable Registers (PWMSEGx) ....................... A-82
PWM Polarity Select Registers (PWMPOLx) ......................... A-83
PWM Channel Duty Control Registers
(PWMAx, PWMBx) ........................................................... A-84
PWM Channel Low Duty Control Registers
(PWMALx, PWMBLx) ...................................................... A-84
PWM Dead Time Registers (PWMDTx) ............................... A-85
To Next Page
Loading...
