ADSP-21368 SHARC Processor Hardware Reference 4-49
Digital Audio/Digital Peripheral Interfaces
Figure 4-40. SRU_PBEN3
Table 4-9. Group F Sources—Pin Output Enable
Selection Code Source Signal Description (Output Source)
000000 (0x0) LOW Select logic level low (0)
000001 (0x1) HIGH Select logic level high (1)
000010 (0x2) MISCA0_O Assign miscellaneous control A0 output to a pin
000011 (0x3) MISCA1_O Assign miscellaneous control A1 output to a pin
000100 (0x4) MISCA2_O Assign miscellaneous control A2 output to a pin
000101 (0x5) MISCA3_O Assign miscellaneous control A3 output to a pin
000110 (0x6) MISCA4_O Assign miscellaneous control A4 output to a pin
000111 (0x7) MISCA5_O Assign miscellaneous control A5 output to a pin
001000 (0x8) SPORT0_CLK_PBEN_O Select serial port 0 clock output enable
001001 (0x9) SPORT0_FS_PBEN_O Select serial port 0 frame sync output enable
001010 (0xA) SPORT0_DA_PBEN_O Select serial port 0 data channel A output enable
001011 (0xB) SPORT0_DB_PBEN_O Select serial port 0 data channel B output enable
001100 (0xC) SPORT1_CLK_PBEN_O Select serial port 1 clock output enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1000111010111000
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1111101111001101
DAI Port 20 Pin Buffer Enable Input
PBEN20_I
DAI Port 18 Pin Buffer Enable Input
PBEN18_I
DAI Port 16
Pin Buffer Enable Input
PBEN16_I
DAI Port 19
Pin Buffer Enable Input
PBEN19_I
DAI Port 17 Pin Buffer Enable Input
PBEN17_I
SRU_PBEN3 (0x247B)
PBEN18_I
DAI Port 18
Pin Buffer Enable Input
Reset = 0x1D71F79B
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