ADSP-21368 SHARC Processor Hardware Reference xxix
Contents
Master Control Register (TWIMCTL) ................................ A-136
Master Address Register (TWIMADDR) ............................. A-139
Master Status Register (TWIMSTAT) ................................. A-140
FIFO Control Register (TWIFIFOCTL) ............................. A-143
FIFO Status Register (TWIFIFOSTAT) .............................. A-145
Interrupt Source Register (TWIIRPTL) .............................. A-147
Interrupt Enable Register (TWIIMASK) ............................. A-150
8-Bit Transmit FIFO Register (TXTWI8) ........................... A-152
16-Bit Transmit FIFO Register (TXTWI16) ....................... A-153
8-Bit Receive FIFO Register (RXTWI8) .............................. A-154
16-Bit Receive FIFO Register (RXTWI16) .......................... A-154
Precision Clock Generator Registers ......................................... A-155
Control Registers (PCG_CTLxx) ........................................ A-155
PCG Pulse Width Registers ................................................ A-158
PCG Frame Synchronization Registers (PCG_SYNCx) ........ A-160
Peripheral Interrupt Priority Control Registers .......................... A-164
Peripheral Interrupt Priority Control
Registers (PICRx) ............................................................ A-164
Peripheral Interrupt Priority0 Control
Register (PICR0) ......................................................... A-167
Peripheral Interrupt Priority1 Control
Register (PICR1) ......................................................... A-168
Peripheral Interrupt Priority2 Control
Register (PICR2) ......................................................... A-169
Peripheral Interrupt Priority3 Control
Register (PICR3) ......................................................... A-170
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