Contents
xxviii ADSP-21368 SHARC Processor Hardware Reference
DPI Resistor Pull-up Enable Register
(DPI_PIN_PULLUP) ...................................................... A-115
DPI Pin Buffer Status Register (DPI_PIN_STAT) ................ A-116
DPI Interrupt Controller Registers ...................................... A-116
UART Control and Status Registers .......................................... A-118
Line Control Registers (UARTxLCR) .................................. A-118
Line Status Registers (UARTxLSR) ...................................... A-120
Transmit Hold Registers (UARTxTHR) ............................... A-121
Receive Buffer Registers (UARTxRBR) ................................ A-122
Interrupt Enable Registers (UARTxIER) .............................. A-123
Interrupt Identification Registers (UARTxIIR) ..................... A-124
Divisor Latch Registers (UARTxDLL, UARTxDLH) ........... A-125
Scratch Registers (UARTxSCR) ........................................... A-126
Mode Registers (UARTxMODE) ......................................... A-126
UART DMA Registers ........................................................ A-127
DMA Control Registers (UARTxTXCTL,
UARTxRXCTL) .......................................................... A-128
DMA Status Registers (UARTxTXSTAT,
UARTxRXSTAT) ........................................................ A-129
Two Wire Interface Registers ..................................................... A-130
Master Internal Time Register (TWIMITR) ........................ A-131
Clock Divider Register (TWIDIV) ...................................... A-132
Slave Mode Control Register (TWISCTL) ........................... A-133
Slave Address Register (TWISADDR) ................................. A-135
Slave Status Register (TWISSTAT) ...................................... A-135
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