ADSP-21368 SHARC Processor Hardware Reference 6-43
Serial Peripheral Interface Ports
Listing 6-3. SPI DMA Chaining Example
/* SPI Control registers */
#define SPICTL (0x1000) /* SPI Control register */
#define SPIFLG (0x1001) /* SPI Flag register */
#define SPIBAUD (0x1005) /* SPI baud setup register */
/* SPI DMA registers */
#define IISPI (0x1080) /* Internal DMA address */
#define IMSPI (0x1081) /* Internal DMA access modifier */
#define CSPI (0x1082) /* Number of words to transfers */
#define CPSPI (0x1083) /* Points to next DMA parameters*/
#define SPIDMAC (0x1084) /* SPI DMA control register */
/*SPIFLG bits */
#define DS0EN (0x0001) /* enable SPI device select 0 */
#define SPIFLG0 (0x0100) /* manually set SPIFLG0 state */
#define SPIFLG1 (0x0200) /* manually set SPIFLG1 state */
#define SPIFLG2 (0x0400) /* manually set SPIFLG2 state */
#define SPIFLG3 (0x0800) /* manually set SPIFLG3 state */
/*SPIDMAC bits */
#define SPIDEN (0x0001) /* enable DMA on the SPI port */
#define SPIRCV (0x0002) /* set to have DMA receive */
#define SPICHEN (0x0010) /* set to enable DMA chaining */
/*SPICTL bits */
#define TIMOD2 (0x0002) /* Use DMA for transfers */
#define SENDZ (0x0004) /* when TXSPI empty, MOSI sends 0 */
#define WL32 (0x0100) /* SPI Word Length = 32 */
#define SPIMS (0x1000) /* SPI Master if 1, Slave if 0 */
#define SPIEN (0x4000) /* SPI port Enable */
#define CLKPL (0x0800) /* if 1, rising edge samples data */
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