Programming Examples
6-44 ADSP-21368 SHARC Processor Hardware Reference
#define CPHASE (0x0400) /* if 1, data's sampled on second
(middle) edge of SPICLK cycle*/
/*========================================================*/
.section/dm seg_dmda;
/* Destinations for incoming data */
.var dest_bufC[8];
.var dest_bufB[8];
.var dest_bufA[8];
/* Transfer Control Blocks (TCB's) */
.var first_tcb[] =
(0x7FFFF&second_tcb + 3), /* for CPSPI (next tcb) */
LENGTH(dest_bufB), /* for CSPI (next count) */
1, /* for IMSPI (next modify) */
dest_bufB; /* for IISPI (next index) */
.var second_tcb[] = 0, /* null CPSPI ends chain */
LENGTH(dest_bufC), /* count for final DMA */
1, /* IM for final DMA */
dest_bufC; /* II for final DMA */
/* NOTE: Chain Pointer registers must point to the LAST
location in the TCB, "tcb + 3". */
/*Main code section */
.global _main;
.section/pm seg_pmco;
_main:
/* clear SPI settings */
r0 = 0;
dm(SPICTL) = r0;
dm(SPIFLG) = r0;
dm(SPIDMAC) = r0;
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