Analog Devices SHARC ADSP-21368 - Page 7

ADSP-21368 SHARC Processor Hardware Reference vii
Contents
SDRAM Control Status Register (SDSTAT) ........................... 3-49
SDRAM Refresh Rate Control Register (SDRRC) .................. 3-49
SDRAM Initialization ........................................................... 3-51
SDRAM Address Mapping .................................................... 3-51
SDRAM Controller Address Mapping ............................... 3-58
SDC Operation ..................................................................... 3-58
Single Bank Operation ...................................................... 3-60
Multibank Operation (ADSP-2137x Processors) ................ 3-60
Data Mask (DQM) ........................................................... 3-61
SDC Configuration ............................................................... 3-61
SDC Commands ................................................................... 3-63
Load Mode Register .......................................................... 3-64
Single Bank Activation ...................................................... 3-65
Multibank Activation (ADSP-2137x Processors) ................ 3-66
Single Precharge (ADSP-2137x Processors) ........................ 3-66
Precharge All ..................................................................... 3-66
Read/Write ....................................................................... 3-67
Read/Write (ADSP-2137x Processors) ............................... 3-69
Burst Stop (ADSP-2137x Processors) ................................. 3-69
Auto-Refresh ..................................................................... 3-70
Self-Refresh Mode ............................................................. 3-70
No Operation/Command Inhibit ...................................... 3-71
Changing System Clock During Runtime .......................... 3-73