Contents
viii ADSP-21368 SHARC Processor Hardware Reference
SDRAM Timing ................................................................... 3-74
SDRAM Read Optimization ............................................. 3-75
External Memory Access Restrictions ................................ 3-78
Shared Memory Interface ............................................................ 3-79
Shared Memory Bus Arbitration ............................................ 3-79
Bus Arbitration Protocol ................................................... 3-82
Bus Arbitration Priority (RPBA) ....................................... 3-86
Bus Mastership Time-out .................................................. 3-87
Bus Synchronization After Reset ............................................ 3-88
Bus Synchronization Notes ............................................... 3-91
Bus Lock and Semaphores ..................................................... 3-92
Shared Memory Interface Status ........................................ 3-93
Shared Memory and the SDRAM Controller ......................... 3-94
Shared Memory Booting ....................................................... 3-94
DIGITAL AUDIO/DIGITAL PERIPHERAL INTERFACES
Structure of the Interfaces ............................................................. 4-2
DAI/DPI System Design ............................................................... 4-3
Signal Routing Units .................................................................... 4-8
Connecting Peripherals ........................................................... 4-8
Pin Interface ......................................................................... 4-10
Pin Buffers as Signal Output Pins .......................................... 4-11
Pin Buffers as Signal Input Pins ............................................. 4-12
Bidirectional Pin Buffers ....................................................... 4-13
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