ADSP-21368 SHARC Processor Hardware Reference A-137
Register Reference
Table A-57. Master Control Register Bit Descriptions
Bit Name Description
0TWIMEN Master Mode Enable. Clears itself at the completion of a transfer.
This includes transfers terminated due to errors.
0 = Master mode functionality is disabled. If MEN is cleared during
operation, the transfer is aborted and all logic associated with master
mode transfers are reset. Serial data and serial clock (SDA, SCL) are
no longer driven. Write 1-to-clear status bits are not effected.
1 = Master mode functionality is enabled. A START condition is
generated if the bus is idle.
1TWIMLENMaster Address Length.
0 = Address is 7-bit
1 = Reserved. Setting this bit to one causes unpredictable behavior
2TWIMDIR Master Transfer Direction.
0 = The initiated transfer is master transmit
1 = The initiated transfer is master receive
3TWIFAST Fast Mode.
0 = Standard mode timing specifications in use
1 = Fast mode timing specifications in use
4TWISTOP Issue STOP Condition.
0 = Normal transfer operation
1 = The transfer concludes as soon as possible avoiding any error
conditions (as if data transfer count had been reached) and at that
time the interrupt source register is updated along with any associ-
ated status bits.
5TWIRSTART Repeat START.
0 = Transfer concludes with a STOP condition
1 = Issue a repeat START condition at the conclusion of the current
transfer (DCNT = 0) and begin the next transfer. The current trans-
fer is concluded with updates to the appropriate status and interrupt
bits. If errors occurred during the previous transfer, a repeat START
does not occur. In the absence of any errors, master enable (MEN)
does not clear itself on a repeat start.
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