ADSP-21368 SHARC Processor Hardware Reference A-141
Register Reference
Table A-58. Master Status Register Bit Descriptions
Bit Name Description
0TWIMPROG Master Transfer In Progress.
0 = Currently no transfer is taking place. This can occur once
a transfer is complete or while an enabled master is waiting
for an idle bus.
1 = A master transfer is in progress.
1TWILOSTLost Arbitration.
0 = The current transfer has not lost arbitration with another
master.
1 = The current transfer was aborted due to the loss of arbi-
tration with another master. This bit is cleared by writing a 1
to its bit location.
2 TWIANAK Address Not Acknowledged.
0 = The current master transfer has not detected a NAK dur-
ing addressing.
1 = The current master transfer was aborted due to the detec-
tion of a NAK during the address phase of the transfer. This
bit is cleared by writing a 1 to its bit location.
3 TWIDNAK Data Not Acknowledged.
0 = The current master transfer has not detected a NAK dur-
ing data transmission.
1 = The current master transfer was aborted due to the detec-
tion of a NAK during data transmission. This bit is cleared
by writing a 1 to its bit location.
4 TWIRERR Buffer Read Error.
0 = The current master transmit has not detected a buffer
read error.
1 = The current master transfer was aborted due to a transmit
buffer read error. At the time data was required by the trans-
mit shift register, the buffer was empty. This bit is cleared by
writing a 1 to its bit location.
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