Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1284 of 1823
Jul 31, 2019
RX23W Group 36. CAN Module (RSCAN)
36.9.3 Communication Speed Setting
Set the CAN communication speed for each channel using the fCAN, baud rate prescaler division value
(CFGL.BRP[9:0] bits), and Tq count per bit time.
Figure 36.18 shows the CAN clock control block diagram, and Table 36.13 shows an example of the communication
speed setting.
Figure 36.18 CAN Clock Control Block Diagram
Note: Values in ( ) are baud rate prescaler division values.
Table 36.13 Example of Communication Speed Setting
Communication Speed
fCAN
16 MHz 8 MHz
1 Mbps 8 Tq (2)
16 Tq (1)
8 Tq (1)
500 kbps 8 Tq (4)
16 Tq (2)
8 Tq (2)
16 Tq (1)
250 kbps 8 Tq (8)
16 Tq (4)
8 Tq (4)
16 Tq (2)
83.3 kbps 8 Tq (24)
16 Tq (12)
8 Tq (12)
16 Tq (6)
33.3 kbps 8 Tq (60)
10 Tq (48)
16 Tq (30)
20 Tq (24)
8 Tq (30)
10 Tq (24)
16 Tq (15)
20 Tq (12)
CANMCLK
fCANTQ
0
1
DCS
Baud rate prescaler
1/(P + 1)
PCLK
P = 0 to 1023
BRP[9:0]
fCAN
fCAN
Baud rate prescaler division value × (Tq count of 1 bit time)
Communication speed =
DCS: Bit in the GCFGL register
BRP[9:0]: Bits in the CFGL register
fCAN: CAN clock
fCANTQ: CANTq clock
1/2

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English