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R01UH0823EJ0100 Rev.1.00 Page 278 of 1823

Jul 31, 2019

RX23W Group 15. Interrupt Controller (ICUb)

15.2.9 IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0)

FLTENi Bit (IRQi Digital Filter Enable) (i = 0, 1, and 4 to 7)

This bit enables the digital filter used for the IRQi pin.

The digital filter is enabled when the FLTENi bit is 1, and disabled when the FLTENi bit is 0.

The IRQi pin level is sampled at the sampling clock cycle specified with the IRQFLTC0.FCLKSELi[1:0] bits. When the

sampled level matches three times, the output level from the digital filter changes.

For details of the digital filter, see

section 15.4.7, Digital Filter.

Address(es): ICU.IRQFLTE0 0008 7510h

b7 b6 b5 b4 b3 b2 b1 b0

FLTEN

——

FLTEN

Value after reset:

00000000

Bit Symbol Bit Name Description R/W

b0 FLTEN0 IRQ0 Digital Filter Enable 0: Digital filter is disabled

1: Digital filter is enabled

R/W

b1 FLTEN1 IRQ1 Digital Filter Enable R/W

b3, b2 — Reserved These bits are read as 0. The write value should be 0. R/W

b4 FLTEN4 IRQ4 Digital Filter Enable 0: Digital filter is disabled

1: Digital filter is enabled

R/W

b5 FLTEN5 IRQ5 Digital Filter Enable R/W

b6 FLTEN6 IRQ6 Digital Filter Enable R/W

b7 FLTEN7 IRQ7 Digital Filter Enable R/W

Renesas RX Series User Manual

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