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Renesas RX Series User Manual

Renesas RX Series
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R01UH0823EJ0100 Rev.1.00 Page 934 of 1823
Jul 31, 2019
RX23W Group 32. USB 2.0 Host/Function Module (USBc)
32.3.4 Pipe Control
Table 32.15 lists the pipe settings for the USB. With USB data transfer, data transfer is carried out using the pipe that the
software has associated with the endpoint. The USB has ten pipes that are used for data transfer.
Appropriate settings should be made for each of the pipes according to the specifications of the system.
Table 32.15 Pipe Settings
Register
Name Bit Name Setting Remarks
DCPCFG
PIPECFG
TYPE[1:0] Specifies the transfer type PIPE1 to PIPE9: Can be set
BFRE Selects the BRDY interrupt
mode
PIPE1 to PIPE5: Can be set
DBLB Selects double buffer mode PIPE1 to PIPE5: Can be set
DIR Selects transfer direction IN or OUT can be set
EPNUM[3:0] Endpoint number PIPE1 to PIPE9: Can be set
A value other than 0000b should be set when the pipe is used.
SHTNAK Selects disabled state for
pipe when transfer ends
PIPE1 and PIPE2: Can be set (only when bulk transfer has been
selected)
PIPE3 to PIPE5: Can be set
DCPMAXP
PIPEMAXP
DEVSEL[3:0] Selects a device Referenced only when the host controller is selected.
MXPS[8:0] Maximum packet size Compliant with USB Specification 2.0.
PIPEPERI IFIS Buffer flush PIPE1 and PIPE2: Can be set (only when isochronous transfer has
been selected)
PIPE3 to PIPE9: Cannot be set
IITV[2:0] Interval counter PIPE1 and PIPE2: Can be set (only when isochronous transfer has
been selected)
PIPE3 to PIPE5: Cannot be set
PIPE6 to PIPE9: Can be set (only when the host controller has been
selected)
DCPCTR
PIPEnCTR
BSTS Buffer status For the DCP, receive buffer status and transmit buffer status are
switched with the ISEL bit.
INBUFM IN buffer monitor Available only for PIPE1 to PIPE5.
SUREQ SETUP request Can be set only for the DCP.
Can be controlled only when the host controller has been selected.
SUREQCLR SUREQ clear Can be set only for the DCP.
Can be controlled only when the host controller has been selected.
ATREPM Auto response mode PIPE1 to PIPE5: Can be set
Can be set only when the function controller has been selected.
ACLRM Auto buffer clear PIPE1 to PIPE9: Can be set
SQCLR Sequence clear Clears the data toggle bit.
SQSET Sequence set Sets the data toggle bit.
SQMON Sequence monitor Monitors the data toggle bit.
PBUSY Pipe busy status
PID[1:0] Response PID Refer to section 32.3.4.6, Response PID.
PIPEnTRE TRENB Transaction counter enable PIPE1 to PIPE5: Can be set
TRCLR Current transaction counter
clear
PIPE1 to PIPE5: Can be set
PIPEnTRN
Transaction counter
PIPE1 to PIPE5: Can be set

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Renesas RX Series Specifications

General IconGeneral
CoreRXv1, RXv2, RXv3
Flash MemoryUp to 8 MB
RAMUp to 1 MB
Operating Voltage1.62V to 5.5V
Operating Temperature-40°C to +85°C or +105°C
PackageBGA, LQFP
ADC Resolution12-bit
DAC Resolution12-bit
Communication InterfacesSCI, SPI, I2C, USB, Ethernet, CAN
Architecture32-bit
Security FeaturesMemory Protection Unit (MPU)

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