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R01UH0823EJ0100 Rev.1.00 Page 845 of 1823

Jul 31, 2019

RX23W Group 31. Independent Watchdog Timer (IWDTa)

31.3.1.2 Auto-Start Mode

When the IWDTSTRT bit in option function select register 0 (OFS0) is 0, auto-start mode is selected, and the IWDTCR,

IWDTRCR, and IWDTCSTPR registers are disabled.

Within the reset state, the clock divide ratio, window start and end positions, timeout period, reset output or interrupt

request output, and counter stop control at transitions to low power consumption states are set using the values specified

in the OFS0 register. When the reset is released, the counter automatically starts counting down from the value selected

by the OFS0.IWDTTOPS[1:0] bits.

After that, as long as the program continues normal operation and the counter is refreshed in the refresh-permitted period,

the value in the counter is re-set each time the counter is refreshed and counting down continues. The IWDT does not

output the reset signal as long as this continues. However, if the counter underflows because refreshing of the counter is

not possible due to the program having entered crashed execution or if a refresh error occurs due to refreshing outside the

refresh-permitted period, the IWDT outputs the reset signal or non-maskable interrupt request (WUNI). After the reset

signal or non-maskable interrupt request (WUNI) is generated, the counter reloads the timeout period after counting for

one cycle, and restarts counting. Set the OFS0.IWDTRSTIRQS bit to select either reset output or interrupt request

output.

Figure 31.4 shows an example of operation under the following conditions.

 Auto-start mode (OFS0.IWDTSTRT = 0)

 Non-maskable interrupt request output is enabled (OFS0.IWDTRSTIRQS = 0)

 The window start position is 75% (OFS0.IWDTRPSS[1:0] = 10b)

 The window end position is 25% (OFS0.IWDTRPES[1:0] = 10b)

Renesas RX Series User Manual

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