R01UH0823EJ0100 Rev.1.00 Page 168 of 1823
Jul 31, 2019
RX23W Group 9. Clock Generation Circuit
9. Clock Generation Circuit
9.1 Overview
This MCU incorporates a clock generation circuit.
Table 9.1 lists the specifications of the clock generation circuit. Figure 9.1 shows a block diagram of the clock
generation circuit.
Table 9.1 Specifications of Clock Generation Circuit (1/2)
Item Specification
Uses Generates the system clock (ICLK) to be supplied to the CPU, DMAC, DTC, ROM, and RAM.
Generates the peripheral module clocks (PCLKA, PCLKB, and PCLKD) to be supplied to
peripheral modules.
The peripheral module clock PCLKA is the operating clock for the MTU2, the peripheral module
clock PCLKD is for the S12AD, and PCLKB is for other modules.
Generates the FlashIF clock (FCLK) to be supplied to the FlashIF.
Generates the USB clock (UCLK) to be supplied to the USB.
Generates the CAC clock (CACCLK) to be supplied to the CAC.
Generates the RTC-dedicated sub-clock (RTCSCLK) to be supplied to the RTC.
Generates the IWDT-dedicated low-speed clock (IWDTCLK) to be supplied to the IWDT.
Generates the CAN clock (CANMCLK) to be supplied to the RSCAN.
Generates the SSI clock (SSISCK) to be supplied to the SSI.
Generates the LPT clock (LPTCLK) to be supplied to the LPT.
Generation of Bluetooth-dedicated clock (BLECK)
Generation of Bluetooth-dedicated low speed clock (BLELOCO)
Operating frequencies*
1
ICLK: 54 MHz (max)
PCLKA: 54 MHz (max)
PCLKB: 32 MHz (max)
PCLKD: 54 MHz (max)
FCLK: 1 to 32 MHz (for programming and erasing the ROM and E2 DataFlash)
32 MHz (max) (for reading from the E2 DataFlash)
UCLK: 48 MHz
CACCLK: Same frequency as each oscillator
RTCSCLK: 32.768 kHz
IWDTCLK: 15 kHz
CANMCLK: 20 MHz (max)
SSISCK: 20 MHz (max)
LPTCLK: The same frequency as that of the selected oscillator
BLECK: 32 MHz
BLELOCO: 32.768 kHz
Main clock oscillator*
2
Resonator frequency: 1 to 20 MHz (VCC 2.4 V), 1 to 8 MHz (VCC < 2.4 V)
External clock input frequency: 20 MHz (max)
Connectable resonator or additional circuit: ceramic resonator, crystal
Connection pins: EXTAL, XTAL
Oscillation stop detection function:
When a main clock oscillation stop is detected, the system clock source is switched to LOCO
and MTU output can be forcedly driven to high-impedance.
Drive capacity switching function
Sub-clock oscillator
Resonator frequency: 32.768 kHz
Connectable resonator or additional circuit: crystal
Connection pin: XCIN, XCOUT
Drive capacity switching function
PLL circuit*
3
Input clock source: Main clock
Input pulse frequency division ratio: Selectable from 1, 2, and 4
Input frequency: 4 to 12.5 MHz
Frequency multiplication ratio: Selectable from 4 to 13.5 (increments of 0.5)
VCO oscillation frequency: 24 to 54 MHz (VCC 2.4 V)
USB-dedicated PLL circuit*
3
Input clock source: Main clock
Input pulse frequency division ratio: Selectable from 1, 2, and 4
Input frequency: 4, 6, 8, and 12 MHz
Frequency multiplication ratio: Selectable from 4, 6, 8, and 12
VCO oscillation frequency: 48 MHz (VCC 2.4 V)
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