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R01UH0823EJ0100 Rev.1.00 Page 740 of 1823

Jul 31, 2019

RX23W Group 26. 8-Bit Timer (TMR)

26.3.2 External Counter Reset Input

Figure 26.4 shows an example of the 8-bit timer being used to generate a pulse which is output after a desired delay time

from a TMRIn input.

1. Set the TCR.CCLR[1:0] bits to 11b (cleared by external counter reset signal) and set the TMRIS bit in TCCR to 1

(cleared when the external counter reset signal is high) so that TCNT is cleared at the high level input of the TMRIn

signal.

2. Set the TCSR.OSA[1:0] bits to 10b (high output) and the TCSR.OSB[1:0] bits to 01b (low output), causing the

output to change to high at a compare match of TCORA and to low at a compare match of TCORB.

With these settings, the 8-bit timer provides pulses output at a desired delay time from a TMRIn input determined by

TCORA and with a pulse width determined by TCORB and TCORA.

Figure 26.4 Example of External Counter Reset Signal Input (n = 0 to 2)

TCORA

TCORB

00h

TMRIn

TMOn

TCNT

Renesas RX Series User Manual

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