Renesas RX Series - Serial Extended Mode Register (SEMR)

R01UH0823EJ0100 Rev.1.00 Page 997 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Smaller settings of the SMR.CKS[1:0] bits and larger settings of the BRR register reduce difference in the length of the
1-bit period.
33.2.13 Serial Extended Mode Register (SEMR)
Note 1. Writable only when TE in SCR = 0 and RE in SCR = 0 (both serial transmission and reception are disabled).
The SEMR register is used to select a clock source for 1-bit period in asynchronous mode or a detection method of the
start bit.
Address(es): SCI1.SEMR 0008 A027h, SCI5.SEMR 0008 A0A7h, SCI8.SEMR 0008 A107h, SCI12.SEMR 0008 B307h
b7 b6 b5 b4 b3 b2 b1 b0
RXDES
EL
BGDM NFEN ABCS — BRME — ACS0
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 ACS0 Asynchronous Mode
Clock Source Select
(Valid only in asynchronous mode)
0: External clock input
1: Logical AND of two compare matches output from TMR (valid for SCI5
and SCI12 only)
R/W*
1
b1 — Reserved This bit is read as 0. The write value should be 0. R/W
b2 BRME Bit Rate Modulation
Enable
0: Bit rate modulation function is disabled.
1: Bit rate modulation function is enabled.
R/W*
1
b3 — Reserved This bit is read as 0. The write value should be 0. R/W
b4 ABCS Asynchronous Mode
Base Clock Select
(Valid only in asynchronous mode)
0: Selects 16 base clock cycles for 1-bit period.
1: Selects 8 base clock cycles for 1-bit period.
R/W*
1
b5 NFEN Digital Noise Filter
Function Enable
(In asynchronous mode)
0: Noise cancellation function for the RXDn input signal is disabled.
1: Noise cancellation function for the RXDn input signal is enabled.
(in simple I
2
C mode)
0: Noise cancellation function for the SSCLn and SSDAn input signals is
disabled.
1: Noise cancellation function for the SSCLn and SSDAn input signals is
enabled.
The NFEN bit should be 0 in any mode other than above.
R/W*
1
b6 BGDM Baud Rate Generator
Double-Speed Mode
Select
(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode)
0: Baud rate generator outputs the clock with normal frequency.
1: Baud rate generator outputs the clock with doubled frequency.
R/W*
1
b7 RXDESEL Asynchronous Start Bit
Edge Detection Select
(Valid only in asynchronous mode)
0: The low level on the RXDn pin is detected as the start bit.
1: A falling edge on the RXDn pin is detected as the start bit.
R/W*
1