R01UH0823EJ0100 Rev.1.00 Page 409 of 1823
Jul 31, 2019
RX23W Group 19. Data Transfer Controller (DTCa)
19.10.3 Setting the DTC Transfer Request Enable Register in the Interrupt Controller
(ICU.DTCERn)
The DMA request should not be issued by setting the DMAC trigger select register (ICU.DMRSRm (m = DMAC
channel number)) to the same vector number that has been specified by setting the ICU.DTCERn.DTCE bit to 1 (the
corresponding interrupt source is selected as the DTC trigger). For details on the ICU.DTCERn and ICU.DMRSRm
registers (m = DMAC channel number), refer to
section 15, Interrupt Controller (ICUb).
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