R01UH0823EJ0100 Rev.1.00 Page 1255 of 1823
Jul 31, 2019
RX23W Group 36. CAN Module (RSCAN)
36.2.74 Transmit History Buffer Control Register (THLCC0)
THLE Bit (Transmit History Buffer Enable)
Setting this bit to 1 makes the transmit history buffer available. When data transmission from the buffer selected by the
THLDTE bit has been completed, the transmit history data of transmit messages is stored in the transmit history buffer.
Modify this bit only in channel communication mode or channel halt mode.
THLIE Bit (Transmit History Interrupt Enable)
When the THLIE bit is set to 1 and the source selected by the THLIM bit has occurred, a transmit history interrupt
request is generated. Modify the THLIE bit with the THLE bit set to 0.
THLIM Bit (Transmit History Interrupt Source Select)
This bit is used to select a transmit history interrupt source.
Modify this bit only in channel reset mode.
THLDTE Bit (Transmit History Target Buffer Select)
When this bit is set to 0, the transmit history data of messages transmitted from transmit/receive FIFO buffers is stored in
the transmit history buffer. When this bit is set to 1, the transmit history data of messages transmitted from transmit
buffers and transmit/receive FIFO buffers is stored in the transmit history buffer.
Modify this bit only in channel reset mode.
Address(es): RSCAN0.THLCC0 000A 837Ch
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
—————
THLDT
E
THLIMTHLIE———————THLE
Value after reset:
0000000000000000
Bit Symbol Bit Name Description R/W
b0 THLE Transmit History Buffer Enable 0: Transmit history buffer is not used.
1: Transmit history buffer is used.
R/W
b7 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W
b8 THLIE Transmit History Interrupt Enable 0: Transmit history interrupt is disabled.
1: Transmit history interrupt is enabled.
R/W
b9 THLIM Transmit History Interrupt Source
Select
0: When 6 sets of data have been stored in the transmit
history buffer
1: When a single set of transmit history data has been stored
R/W
b10 THLDTE Transmit History Target Buffer
Select
0: Entry from transmit/receive FIFO buffers
1: Entry from transmit buffers, transmit/receive FIFO buffers
R/W
b15 to b11 — Reserved These bits are read as 0. The write value should be 0. R/W
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