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Renesas RX Series User Manual

Renesas RX Series
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R01UH0823EJ0100 Rev.1.00 Page 1485 of 1823
Jul 31, 2019
RX23W Group 42. Trusted Secure IP (TSIP-Lite)
Figure 42.5 Key Installation Flow Chart
42.2.4 Encryption and Decryption
The procedures for encrypting and decrypting data are given below.
(1) Input the key generation information into the TSIP-Lite, and recover the key data.
(2) Input the data to encrypt or decrypt into the TSIP-Lite. This converts plaintext into ciphertext, and ciphertext into
plaintext.
(3) Read the converted data.
The encryption engine has an input buffer and an output buffer, enabling encryption/decryption to proceed in parallel
with data input/output.
Figure 42.6, Figure 42.7, and Figure 42.8 show the timing diagram, encryption flow, and decryption flow,
respectively.
Figure 42.6 Encryption and Decryption Timing Diagram
START
in encryption engine active mode
Decrypt the user key
Convert to user key generation
information
Output user key generation
information
Input the encrypted user key
TSIP-Lite library uses the unique ID and
a random number
END
in TSIP-Lite enabled mode
State of the
encryption engine
W1 W1 W1 W2 W2 W2 W2W1
Internal
peripheral bus
Input buffer
Encryption Encryption
R1 R1 R1 R1 W3 W3 W3 W3
Output buffer
Block-1
(32 bits × 4)
Block-2
(32 bits × 4)
Block-1
(32 bits × 4)
Block-3
(32 bits × 4)
W1 W2
R1
W3
R2
Encryption
44 cycles or 60 cycles

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Renesas RX Series Specifications

General IconGeneral
CoreRXv1, RXv2, RXv3
Flash MemoryUp to 8 MB
RAMUp to 1 MB
Operating Voltage1.62V to 5.5V
Operating Temperature-40°C to +85°C or +105°C
PackageBGA, LQFP
ADC Resolution12-bit
DAC Resolution12-bit
Communication InterfacesSCI, SPI, I2C, USB, Ethernet, CAN
Architecture32-bit
Security FeaturesMemory Protection Unit (MPU)

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