R01UH0823EJ0100 Rev.1.00 Page 74 of 1823
Jul 31, 2019
RX23W Group 2. CPU
C Flag (Carry Flag)
This flag retains the state of the bit after a carry, borrow, or shift-out has occurred.
Z Flag (Zero Flag)
This flag is set to 1 if the result of an operation is 0; otherwise its value is cleared to 0.
S Flag (Sign Flag)
This flag is set to 1 if the result of an operation is negative; otherwise its value is cleared to 0.
O Flag (Overflow Flag)
This flag is set to 1 if the result of an operation overflows; otherwise its value is cleared to 0.
I Bit (Interrupt Enable)
This bit enables interrupt requests. When a WAIT instruction is executed, the value of this bit becomes 1. It becomes 0
when an exception is accepted.
U Bit (Stack Pointer Select)
This bit specifies the stack pointer as either the ISP or USP. When an exception request is accepted, this bit is set to 0.
When the processor mode is switched from supervisor mode to user mode, this bit is set to 1.
PM Bit (Processor Mode Select)
This bit specifies the processor mode. When an exception is accepted, the value of this bit becomes 0.
IPL[3:0] Bits (Processor Interrupt Priority Level)
The IPL[3:0] bits specify the processor interrupt priority level as one of sixteen levels from zero to fifteen, wherein
priority level zero is the lowest and priority level fifteen the highest. When the priority level of a requested interrupt is
higher than the processor interrupt priority level, the interrupt is enabled. Setting the IPL[3:0] bits to level fifteen (Fh)
disables all interrupt requests. The IPL[3:0] bits are set to level fifteen (Fh) when a non-maskable interrupt is generated.
When interrupts in general are generated, the bits are set to the priority levels of accepted interrupts.
2.2.2.6 Backup PC (BPC)
The backup PC (BPC) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC register.
b31 b0
Value after reset:
Undefined
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