Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 323 of 1823
Jul 31, 2019
RX23W Group 17. Memory-Protection Unit (MPU)
17.2.3 Memory-Protection Enable Register (MPEN)
MPEN Bit (Memory-Protection Enable)
This bit enables or disables the memory protection.
After 1 has been written to this bit, address checking for memory protection by the CPU starts on the execution of a
branch instruction (RTE or RTFI) that shifts operation to the user mode.
Address(es): 0008 6500h
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
————————————————
Value after reset:
0000000000000000
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
———————————————MPEN
Value after reset:
0000000000000000
Bit Symbol Bit Name Function R/W
b0 MPEN Memory-Protection Enable 1: The memory protection is enabled.
0: The memory protection is disabled.
R/W
b31 to b1 — Reserved The read value is 0. The write value should always be 0 R/W

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)