R01UH0823EJ0100 Rev.1.00 Page 1472 of 1823
Jul 31, 2019
RX23W Group 40. SD Host Interface (SDHIa)
40.5.3 Automatic Control of the SDHI Clock Output
As per the SD card specifications, after MCU power-on, 74 cycles of the SDHI clock must be output from the host to the
SD card before the card initialization command (CMD0) can be issued. Therefore, 74 cycles of the SDHI clock should be
output from the SDHI to the SD card before enabling automatic control of the SDHI clock output.
When automatic control of the SDHI clock output is enabled, SDHI clock output stops if the command sequence is ended
by a communication error or timeout. Therefore, if it is necessary to change the internal status of the SD card even after
the command sequence ends, disable automatic control of the SDHI clock output and output the SDHI clock to the SD
card.
40.5.4 Restrictions on Setting the C52PUB Bit During a Multi-Block Write Sequence
During a CMD53 multi-block write sequence, if the SDIOMD.C52PUB bit is set to 1, the SDHI issues CMD52 after the
SD buffer becomes empty. To immediately issue CMD52, perform one of the procedures below to suspend writing to the
SD buffer, and set the C52PUB bit to 1.
Procedure to suspend writing to the SD buffer when not performing DMA transfer (interrupt used)
1. Set the SDIMSK2.BWEM bit to 1 to disable the interrupt, and suspend writing to the SDBUFR register.
2. Set the SDIOMD.C52PUB bit to 1. Then, when the SD buffer becomes empty, the SDHI issues CMD52.
3. After receiving the response for CMD52, set the SDIMSK2.BWEM bit to 0 to enable the interrupt, and resume
writing to the SDBUFR register.
Procedure to suspend writing to the SD buffer when performing DMA transfer
1. Configure settings to perform DMA transfer every [SDSIZE register setting value × n blocks], and suspend writing
to the SDBUFR register before setting the SDIOMD.C52PUB bit (n = 1, 2, ...).
2. Set the SDIOMD.C52PUB bit to 1. Then, when the SD buffer becomes empty, the SDHI issues CMD52.
3. After receiving the response for CMD52, resume DMA transfer to the SDBUFR register.
40.5.5 Note on Setting the SDCLKCR Register
The SDCLKCR register cannot be written when the SDSTS2.SDCLKCREN flag is 0. Set the SDSTS2.SDCLKCREN
flag to 1 before writing to the SDCLKCR register.
40.5.6 Writing to the SDSTOP Register During a Multi-Block Read Sequence
When the SDSTOP.SDBLKCNTEN bit is 1 during a multi-block read sequence, if the SDSTOP.STP bit is set to 1 and
the command sequence is stopped, the command sequence may not be completed depending on when the SDSTOP.STP
bit is set to 1. To avoid this problem, set the SDSTOP.STP bit and the SDSTOP.SDBLKCNTEN bit to 0 simultaneously.
Note that at this time, the SDSTOP.SDBLKCNTEN bit should be set to 0 even if the SDSTS2.SDCLKCREN bit is 0.
If the SDSTOP.SDBLKCNTEN bit is not set to 0, the command sequence can be completed by setting the
SDRST.SDRST bit to 0.
During a CMD53 multi-block transfer, when stopping data transfer by setting the SDIOMD.IOABT bit to 1, the
SDSTOP.SDBLKCNTEN bit should remain set to 1.
40.5.7 Controlling Module Operation
SDHI operation is controlled by setting the MSTPCRD.MSTPD19 bit. Setting the MSTPD19 bit to 0 enables the SDHI;
setting the MSTPD19 bit to 1 disables the SDHI. The SDHI is disabled after a reset. Registers in the SDHI can be
accessed by setting the MSTPD19 bit to 0. Refer to
section 11, Low Power Consumption for details.
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