R01UH0823EJ0100 Rev.1.00 Page 1458 of 1823
Jul 31, 2019
RX23W Group 40. SD Host Interface (SDHIa)
40.3.6.5 Multi-Block Read Command (CMD18)
Figure 40.12 shows an example of issuing the multi-block read command (CMD18).
1. Set the flags in registers SDSTS1 and SDSTS2 to 0.
2. Set the SDHI clock in the SDCLKCR register, and set the interrupt requests to be masked in registers SDIMSK1
and SDIMSK2. Refer to
section 40.5.5 for details on setting the SDCLKCR register. Set the
SDSTOP.SDBLKCNTEN bit to 1, and set the number of transfer blocks in the SDBLKCNT register.
3. After setting the argument field value for CMD18 to the SDARG register, write 0000 0012h to the SDCMD
register. The SDHI issues CMD18 when a value is written to the SDCMD register.
4. When the response is received, the SDSTS1.RSPEND flag becomes 1, and the response end interrupt request is
generated.
5. Set the SDSTS1.RSPEND flag to 0 and read the response stored in the SDRSP54 register. If the read response is in
error, set the SDSTOP.STP bit to 1, and the command sequence can be stopped. When the SDSTOP.STP bit is set to
1, the SDHI automatically issues CMD12, and the response is received. At this point, the SDSTS1.ACEND flag
becomes 1, and if the access end interrupt request is enabled, the access end interrupt request is generated. Next, set
the SDSTS1.ACEND flag to 0 and read the response.
6. After the response is received, set the SDIMSK1.ACENDM bit to 0, and set the SDIMSK2.BREM bit to 0.
7. After receiving one block of data from the SD card, the SDSTS2.BRE bit becomes 1, and the BRE interrupt request
is generated.
8. Set the SDSTS2.BRE flag to 0, and read the amount of data set in the SDSIZE.LEN[9:0] bits from the SDBUFR
register. The read access to the SDBUFR register repeats for the amount of transfer blocks set in the SDBLKCNT
register. Also, while reading the SDBUFR register, data reception may cause a communication error or timeout to
occur. After the amount of transfer blocks set in the SDBLKCNT register have been read, the SDHI automatically
issues CMD12, and the response is received. At this time, the SDHI automatically writes 0000 0000h to the
SDARG register.
9. When all blocks have been received and the CMD12 response is received, the SDSTS1.ACEND flag becomes 1 and
the access end interrupt request is generated.
10. Set the SDSTS1.ACEND flag to 0 and read the response.
Perform error processing (clear the interrupt flag) if a communication error or timeout occurs.
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