R01UH0823EJ0100 Rev.1.00 Page 284 of 1823
Jul 31, 2019
RX23W Group 15. Interrupt Controller (ICUb)
15.2.13 Non-Maskable Interrupt Status Clear Register (NMICLR)
Note 1. Only 1 can be written to this bit.
NMICLR Bit (NMI Clear)
Writing 1 to the NMICLR bit clears the NMISR.NMIST flag. This bit is read as 0.
OSTCLR Bit (OST Clear)
Writing 1 to the OSTCLR bit clears the NMISR.OSTST flag. This bit is read as 0.
WDTCLR Bit (WDT Clear)
Writing 1 to the WDTCLR bit clears the NMISR.WDTST flag. This bit is read as 0.
IWDTCLR Bit (IWDT Clear)
Writing 1 to the IWDTCLR bit clears the NMISR.IWDTST flag. This bit is read as 0.
LVD1CLR Bit (LVD1 Clear)
Writing 1 to the LVD1CLR bit clears the NMISR.LVD1ST flag. This bit is read as 0.
VBATCLR Bit (VBAT Clear)
Writing 1 to the VBATCLR bit clears the NMISR.VBATST flag. This bit is read as 0.
Address(es): ICU.NMICLR 0008 7582h
b7 b6 b5 b4 b3 b2 b1 b0
—
VBATC
LR
—
LVD1C
LR
IWDTC
LR
WDTCL
R
OSTCL
R
NMICL
R
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 NMICLR NMI Clear This bit is read as 0. Writing 1 to this bit clears the NMISR.NMIST flag.
Writing 0 to this bit has no effect.
R/(W)
*
1
b1 OSTCLR OST Clear This bit is read as 0. Writing 1 to this bit clears the NMISR.OSTST flag.
Writing 0 to this bit has no effect.
R/(W)
*
1
b2 WDTCLR WDT Clear This bit is read as 0. Writing 1 to this bit clears the NMISR.WDTST flag.
Writing 0 to this bit has no effect.
R/(W)
*
1
b3 IWDTCLR IWDT Clear This bit is read as 0. Writing 1 to this bit clears the NMISR.IWDTST
flag. Writing 0 to this bit has no effect.
R/(W)
*
1
b4 LVD1CLR LVD1 Clear This bit is read as 0. Writing 1 to this bit clears the NMISR.LVD1ST flag.
Writing 0 to this bit has no effect.
R/(W)
*
1
b5 — Reserved This bit is read as 0. The write value should be 0. R/W
b6 VBATCLR VBAT Clear This bit is read as 0. Writing 1 to this bit clears the NMISR.VBATST
flag. Writing 0 has no effect.
R/(W)
*
1
b7 — Reserved This bit is read as 0. The write value should be 0. R/W
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