Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1164 of 1823
Jul 31, 2019
RX23W Group 35. I
2
C-bus Interface (RIICa)
35.7 Address Match Detection
The RIIC can set three unique slave addresses in addition to the general call address and host address, and also can set 7-
bit or 10-bit slave addresses.
35.7.1 Slave-Address Match Detection
The RIIC can set three unique slave addresses, and has a slave address detection function for each unique slave address.
When the ICSER.SARyE bit (y = 0 to 2) is set to 1, the slave addresses set in registers SARUy and SARLy (y = 0 to 2)
can be detected.
When the RIIC detects a match of the set slave address, the corresponding ICSR1.AASy flag (y = 0 to 2) is set to 1 at the
rising edge of the ninth SCL clock cycle, and the ICSR2.RDRF flag or the ICSR2.TDRE flag is set to 1 by the following
R/W# bit. This causes a receive data full interrupt (RXI) or transmit data empty interrupt (TXI) to be generated. The
AASy flag is used to identify which slave address has been specified.
Figure 35.24 to Figure 35.26 show the AASy flag set timing in three cases.
Figure 35.24 AASy Flag Set Timing with 7-Bit Address Format Selected
TDRE
AASy
S 1 234567
7-bit slave address
8
W
1
8
R
9
ACK
TRS
9
ACK
BBSY
TDRE
AASy
TRS
BBSY
RDRF
RDRF
234567
Data (DATA 1)
8 9
ACK
S 1 234567
1 2345
234567 8 9
ACK
1
Read ICDRR register
(Dummy read [7-bit address])
Address match
[7-bit address format: Slave reception]
1 2345
[7-bit address format: Slave transmission]
7-bit slave address
Data (DATA 2)
Data (DATA 1) Data (DATA 2)
Receive data (7-bit address) Receive data (DATA 1)
Read ICDRR register
(DATA 1)
Write data to ICDRT
register (DATA 3)
Write data to ICDRT
register (DATA 1)
Write data to ICDRT
register (DATA 2)
Transmit data (DATA 2)Transmit data (DATA 1)
Address match
SCL0
SDA0
SCL0
SDA0

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English