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Renesas RX Series User Manual

Renesas RX Series
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R01UH0823EJ0100 Rev.1.00 Page 86 of 1823
Jul 31, 2019
RX23W Group 2. CPU
2.5.2 Access to I/O Registers
The addresses of I/O registers are fixed, and this is regardless of whether the setting is for little endian or big endian.
Accordingly, changes to the endian do not affect access to I/O registers. For the arrangements of I/O registers, refer to the
descriptions of registers in the relevant sections.
2.5.3 Notes on Access to I/O Registers
Ensure that access to I/O registers is in accord with the following rules.
With I/O registers for which a bus width of eight bits is indicated, use instructions having operands of the same
width (eight bits). That is, access these registers by using instructions with .B as the size specifier (.size), or with .B
or .UB as the size-extension specifier (.memex).
With I/O registers for which a bus width of 16 bits is indicated, use instructions having operands of the same width
(16 bits). That is, access these registers by using instructions with .W as the size specifier (.size), or with .W or .UW
as the size-extension specifier (.memex).
With I/O registers for which a bus width of 32 bits is indicated, use instructions having operands of the same width
(32 bits). That is, access these registers by using instructions with .L as the size specifier (.size), or with .L size-
extension specifier (.memex).
Table 2.10 8-Bit Read Operations when Big Endian has been Selected
Operation
Address of src
Reading an 8-bit unit
from address 0
Reading an 8-bit unit
from address 1
Reading an 8-bit unit
from address 2
Reading an 8-bit unit
from address 3
Address 0 Transfer to LL
Address 1 Transfer to LL
Address 2 Transfer to LL
Address 3 Transfer to LL
Table 2.11 8-Bit Write Operations when Little Endian has been Selected
Operation
Address of dest
Writing an 8-bit unit to
address 0
Writing an 8-bit unit to
address 1
Writing an 8-bit unit to
address 2
Writing an 8-bit unit to
address 3
Address 0 Transfer from LL
Address 1 Transfer from LL
Address 2 Transfer from LL
Address 3 Transfer from LL
Table 2.12 8-Bit Write Operations when Big Endian has been Selected
Operation
Address of dest
Writing an 8-bit unit to
address 0
Writing an 8-bit unit to
address 1
Writing an 8-bit unit to
address 2
Writing an 8-bit unit to
address 3
Address 0 Transfer from LL
Address 1 Transfer from LL
Address 2 Transfer from LL
Address 3 Transfer from LL

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Renesas RX Series Specifications

General IconGeneral
CoreRXv1, RXv2, RXv3
Flash MemoryUp to 8 MB
RAMUp to 1 MB
Operating Voltage1.62V to 5.5V
Operating Temperature-40°C to +85°C or +105°C
PackageBGA, LQFP
ADC Resolution12-bit
DAC Resolution12-bit
Communication InterfacesSCI, SPI, I2C, USB, Ethernet, CAN
Architecture32-bit
Security FeaturesMemory Protection Unit (MPU)

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