R01UH0823EJ0100 Rev.1.00 Page 834 of 1823
Jul 31, 2019
RX23W Group 31. Independent Watchdog Timer (IWDTa)
31. Independent Watchdog Timer (IWDTa)
In this section, “PCLK” is used to refer to PCLKB.
31.1 Overview
The independent watchdog timer (IWDT) can be used to detect programs being out of control.
The user can detect when a program runs out of control if an underflow occurs, by creating a program that refreshes the
IWDT counter before it underflows.
The functions of the IWDT are different from those of the WDT in the following respects.
The divided IWDT-dedicated clock (IWDTCLK) is used as the count source (not affected by the PCLK).
When making a transition to sleep mode, software standby mode, or deep sleep mode, the IWDTCSTPR.SLCSTP
bit or the OFS0.IWDTSLCSTP bit can be used to select whether to stop the counter or not.
Table 31.1 lists the specifications of the IWDT and Figure 31.1 shows a block diagram of the IWDT.
Note 1. Satisfy the frequency of the peripheral module clock (PCLK) 4 × (the frequency of the count source after divide).
Note 2. When the OFS0.IWDTSLCSTP bit is 1 in auto-start mode, and when the IWDTCSTPR.SLCSTP bit is 1 in register start mode.
Table 31.1 IWDT Specifications
Item Description
Count source*
1
IWDT-dedicated clock (IWDTCLK)
Clock divide ratio Divide by 1, 16, 32, 64, 128, or 256
Counter operation Counting down using a 14-bit down-counter
Conditions for starting the
counter
Auto-start mode: Counting automatically starts after a reset is released
Register start mode: Counting is started by refresh operation (writing 00h and then FFh to the
IWDTRR register).
Conditions for stopping the
counter
Reset (the down-counter and other registers return to their initial values)
In low power consumption states (depends on the register setting*
2
)
A counter underflows or a refresh error occurs (only in register start mode)
Window function Window start and end positions can be specified (refresh-permitted and refresh-prohibited periods)
Reset output sources
Down-counter underflows
Refreshing outside the refresh-permitted period (refresh error)
Non-maskable interrupt
sources
Down-counter underflows
Refreshing outside the refresh-permitted period (refresh error)
Reading the counter value The down-counter value can be read by the IWDTSR register.
Event link function (output)
Down-counter underflow event output
Refresh error event output
Output signal (internal signal)
Reset output
Interrupt request output
Sleep mode count stop control output
Auto-start mode
(controlled by option function
select register 0 (OFS0))
Selecting the clock frequency divide ratio after a reset (OFS0.IWDTCKS[3:0] bits)
Selecting the timeout period of the independent watchdog timer (OFS0.IWDTTOPS[1:0] bits)
Selecting the window start position in the independent watchdog timer (OFS0.IWDTRPSS[1:0] bits)
Selecting the window end position in the independent watchdog timer (OFS0.IWDTRPES[1:0] bits)
Selecting the reset output or interrupt request output (OFS0.IWDTRSTIRQS bit)
Selecting the down-count stop function at transition to sleep mode, software standby mode, or
deep sleep mode (OFS0.IWDTSLCSTP bit)
Register start mode
(controlled by the IWDT
registers)
Selecting the clock frequency divide ratio after refreshing (IWDTCR.CKS[3:0] bits)
Selecting the timeout period of the independent watchdog timer (IWDTCR.TOPS[1:0] bits)
Selecting the window start position in the independent watchdog timer (IWDTCR.RPSS[1:0] bits)
Selecting the window end position in the independent watchdog timer (IWDTCR.RPES[1:0] bits)
Selecting the reset output or interrupt request output (IWDTRCR.RSTIRQS bit)
Selecting the down-count stop function at transition to sleep mode, software standby mode, or
deep sleep mode (IWDTCSTPR.SLCSTP bit)
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