R01UH0823EJ0100 Rev.1.00 Page 1204 of 1823
Jul 31, 2019
RX23W Group 36. CAN Module (RSCAN)
36.2.9 Global Configuration Register L (GCFGL)
Modify the GCFGL register only in global reset mode.
TPRI Bit (Transmit Priority Select)
This bit is used to set the transmit priority.
When this bit is set to 0, ID priority is selected and the transmit priority complies with the CAN bus arbitration rule (ISO
11898-1 standard). When this bit is set to 1, transmit buffer number priority is selected and the minimum number of
transmit buffer specified for transmission takes precedence.
DCE Bit (DLC Check Enable)
Setting this bit to 1 makes the DLC check function available. Set the GAFLPHj.GAFLDLC[3:0] bits to 0000b before
setting the DCE bit to 0.
Address(es): RSCAN.GCFGL 000A 8322h
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
— — — TSSS TSP[3:0] — — — DCS MME DRE DCE TPRI
Value after reset:
0000000000000000
Bit Symbol Bit Name Description R/W
b0 TPRI Transmit Priority Select 0: ID priority
1: Transmit buffer number priority
R/W
b1 DCE DLC Check Enable 0: DLC check is disabled.
1: DLC check is enabled.
R/W
b2 DRE DLC Replacement Enable 0: DLC replacement is disabled.
1: DLC replacement is enabled.
R/W
b3 MME Mirror Function Enable 0: Mirror function is disabled.
1: Mirror function is enabled.
R/W
b4 DCS CAN Clock Source Select 0: PCLK
1: CANMCLK (obtained from the main clock)
R/W
b7 to b5 — Reserved These bits are read as 0. The write value should be 0. R/W
b11 to b8 TSP[3:0] Timestamp Clock Source
Division
b11 b8
0000:Not divided
0001:Divided by 2
0010:Divided by 4
0011:Divided by 8
0100:Divided by 16
0101:Divided by 32
0110:Divided by 64
0111:Divided by 128
1000:Divided by 256
1001:Divided by 512
1010:Divided by 1024
1011:Divided by 2048
1100:Divided by 4096
1101:Divided by 8192
1110:Divided by 16384
1111:Divided by 32768
R/W
b12 TSSS Timestamp Clock Source Select 0: PCLK
1: CAN bit time clock
R/W
b15 to b13 — Reserved These bits are read as 0. The write value should be 0. R/W
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