Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 282 of 1823
Jul 31, 2019
RX23W Group 15. Interrupt Controller (ICUb)
15.2.12 Non-Maskable Interrupt Enable Register (NMIER)
Note 1. A 1 can be written to this bit only once, and subsequent write accesses are no longer enabled.
NMIEN Bit (NMI Pin Interrupt Enable)
This bit enables the NMI pin interrupt.
A 1 can be written to this bit only once, and subsequent write accesses are no longer enabled.
Writing 0 to this bit is disabled.
OSTEN Bit (Oscillation Stop Detection Interrupt Enable)
This bit enables the oscillation stop detection interrupt.
A 1 can be written to this bit only once, and subsequent write accesses are no longer enabled.
Writing 0 to this bit is disabled.
WDTEN Bit (WDT Underflow/Refresh Error Enable)
This bit enables the WDT underflow/refresh error interrupt.
A 1 can be written to this bit only once, and subsequent write accesses are no longer enabled.
Writing 0 to this bit is disabled.
IWDTEN Bit (IWDT Underflow/Refresh Error Enable)
This bit enables the IWDT underflow/refresh error interrupt.
A 1 can be written to this bit only once, and subsequent write accesses are no longer enabled.
Writing 0 to this bit is disabled.
LVD1EN Bit (Voltage Monitoring 1 Interrupt Enable)
This bit enables the voltage monitoring 1 interrupt.
A 1 can be written to this bit only once, and subsequent write accesses are no longer enabled.
Writing 0 to this bit is disabled.
Address(es): ICU.NMIER 0008 7581h
b7 b6 b5 b4 b3 b2 b1 b0
—
VBATE
N
—
LVD1E
N
IWDTE
N
WDTE
N
OSTEN NMIEN
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 NMIEN NMI Pin Interrupt Enable 0: NMI pin interrupt is disabled
1: NMI pin interrupt is enabled
R/(W)
*
1
b1 OSTEN Oscillation Stop Detection Interrupt
Enable
0: Oscillation stop detection interrupt is disabled
1: Oscillation stop detection interrupt is enabled
R/(W)
*
1
b2 WDTEN WDT Underflow/Refresh Error
Enable
0: WDT underflow/refresh error interrupt is disabled
1: WDT underflow/refresh error interrupt is enabled
R/(W)
*
1
b3 IWDTEN IWDT Underflow/Refresh Error
Enable
0: IWDT underflow/refresh error interrupt is disabled
1: IWDT underflow/refresh error interrupt is enabled
R/(W)
*
1
b4 LVD1EN Voltage Monitoring 1 Interrupt
Enable
0: Voltage monitoring 1 interrupt is disabled
1: Voltage monitoring 1 interrupt is enabled
R/(W)
*
1
b5 — Reserved This bit is read as 0. The write value should be 0. R/W
b6 VBATEN VBATT Voltage Monitoring Interrupt
Enable
0: VBATT voltage monitoring interrupt is disabled
1: VBATT voltage monitoring interrupt is enabled
R/W
*
1
b7 — Reserved This bit is read as 0. The write value should be 0. R/W

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)