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R01UH0823EJ0100 Rev.1.00 Page 298 of 1823

Jul 31, 2019

RX23W Group 15. Interrupt Controller (ICUb)

15.4.3 Selecting Interrupt Request Destinations

Possible settings for the request destination of each interrupt are fixed. That is, settings for request destination other than

those indicated in

Table 15.3, Interrupt Vector Table, are not possible. Do not make an interrupt request destination

setting that is not indicated by a “” in

Table 15.3.

If the DMAC or DTC is selected as the destination for requests from an IRQi pin (i = 0, 1, and 4 to 7), be sure to set the

IRQMD[1:0] bits in IRQCRi for that interrupt to select edge detection.

The following describes how to specify the destinations of interrupt requests.

(1) DMAC Trigger

Make the following settings for each source while the IERm.IENj bit (m = 02h to 1Fh, j = 0 to 7) is 0.

1. Specify the vector number of the desired interrupt in the DMAC trigger select register (DMRSRm) for the required

channel of the DMAC.

2. Set the trigger for the target DMAC channel (DMACm.DMTMD.DCTG[1:0]) to 01b (interrupt module detection).

3. Set the DMAC transfer request enable bit for the target DMAC channel (DMACm.DMCNT.DTE) to 1.

After making the above settings, set the IERm.IENj bit to 1.

In addition, set the DMAC operation enable bit (DMAST.DMST) to 1. The order of making settings for each interrupt

and enabling the DMAC operation enable bit does not matter.

For the DMAC setting procedure, refer to

section 18.3.7, Activating the DMAC in section 18, DMA Controller

(DMACA)

(2) DTC Trigger

Make the following settings for each source while the IERm.IENj bit (m = 02h to 1Fh, j = 0 to 7) is 0.

1. Set the DTC transfer request enable bit in the DTC transfer request enable register (DTCERn.DTCE (n = interrupt

vector number)) for the pertinent source to 1.

After making the above settings, set the IERm.IENj bit to 1.

In addition, set the DTC module start bit (DTCST.DTCST) to 1. The order of making settings for each interrupt and

enabling the DTC module start bit does not matter.

For the DTC setting procedure, refer to

section 19.5, DTC Setting Procedure, in section 19, Data Transfer

Controller (DTCa)

Note 1. Do not set a DTC transfer request enable bit (DTCERn.DTCE) and a DMAC trigger select register (DMRSRm) to

select the same source. Do not select the same source in more than one DMRSRm register.

Renesas RX Series User Manual

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