Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 299 of 1823
Jul 31, 2019
RX23W Group 15. Interrupt Controller (ICUb)
(3) CPU Interrupt Request
If the interrupt request destination is neither the DMAC nor the DTC, the interrupt request is sent to the CPU. Set the
IERm.IENj bit (m = 02h to 1Fh, j = 0 to 7) to 1 while neither the DMAC trigger settings nor the DTC trigger settings
described above are in place.
Table 15.4 shows operation when the DMAC or DTC is the request destination.
Note 1. DISEL for the DMAC is set by the DMACm.DMCSL.DISEL bit; DISEL for the DTC is set by the DTC.MRB.DISEL bit.
Note 2. When the IRn.IR flag is 1, an interrupt request (DTC or DMA transfer request) that is generated again will be ignored.
Note 3. When the DISEL bit is 0, operation with the remaining number of transfer operations being 0 differs according to whether the
source is for the DTC or DMAC.
Note 4. For chain transfer, DTC transfer continues until the last chain transfer ends. Whether a CPU interrupt is generated at the end of
chain transfer, the IRn.IR flag clear timing, and the interrupt request destination after transfer are determined by the state of DISEL
and the remaining transfer count at the end of chain transfer. For the chain transfer, see Table 19.3, Chain Transfer Conditions in
section 19, Data Transfer Controller (DTCa).
The request destination for an interrupt should be changed while the IERm.IENj bit is 0.
When a source is to be changed to an interrupt request or the DMAC trigger source is to be changed while a transfer is
not complete (i.e. while the DMACm.DMCNT.DTE bit has not been cleared) after the settings described under
(1)
DMAC Trigger
have been made, follow the procedure below.
1. For both the source to be withdrawn and the source that will have a new trigger, clear the IENj bits in IERm to 0.
2. Check the state of transfer by the DMAC. If transfer is in progress, wait for its completion.
3. Make the settings described under
(1) DMAC Trigger.
When a source is to be changed to an interrupt request or the DTC transfer information is to be changed while a transfer
is not complete (i.e. while the DTCERn.DTCE bit (n = interrupt vector number) has not been cleared) after the settings
described under
(2) DTC Trigger have been made, follow the procedure below.
1. For both the source to be withdrawn and the source that will have a new trigger, clear the IENj bits in IERm to 0.
2. Check the state of transfer by the DTC. If transfer is in progress, wait for its completion.
3. Make the settings described under
(2) DTC Trigger.
Table 15.4 Operation When Starting the DMAC/DTC
Interrupt
Request
Destination
DISEL
*
1
Remaining
Number of
Transfer
Operations
Operation per
Request IR*
2
Interrupt Request Destination after Transfer
DMAC 1 ≠ 0 DMA transfer →
CPU interrupt
Cleared on interrupt acceptance by the CPU DMAC
= 0 DMA transfer →
CPU interrupt
Cleared on interrupt acceptance by the CPU The DMACm.DMCNT.DTE bit is cleared and the
CPU becomes the destination.
0 ≠ 0 DMA transfer Cleared at the start of DMAC transfer DMAC
= 0 DMA transfer*
3
Cleared at the start of DMAC transfer*
3
The DMACm.DMCNT.DTE bit is cleared and the
CPU becomes the destination.
DTC*
4
1 ≠ 0 DTC transfer →
CPU interrupt
Cleared on interrupt acceptance by the CPU DTC
= 0 DTC transfer →
CPU interrupt
Cleared on interrupt acceptance by the CPU The DTCERn.DTCE bit is cleared and the CPU
becomes the destination.
0 ≠ 0 DTC transfer Cleared at the start of DTC data transfer after
reading DTC transfer information
DTC
= 0 DTC transfer →
CPU interrupt*
3
Cleared on interrupt acceptance by the CPU*
3
The DTCERn.DTCE bit is cleared and the CPU
becomes the destination.

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English