R01UH0823EJ0100 Rev.1.00 Page 341 of 1823
Jul 31, 2019
RX23W Group 18. DMA Controller (DMACA)
18.2.3 DMA Transfer Count Register (DMCRA)
Note: Set the same value for DMCRAH and DMCRAL in repeat transfer mode and block transfer mode.
(1) Normal Transfer Mode (MD[1:0] Bits in DMACm.DMTMD = 00b)
DMCRAL functions as a 16-bit transfer counter.
The number of transfer operations is one when the setting is 0001h, and 65535 when it is FFFFh. The value is
decremented by one each time data is transferred.
When the setting is 0000h, no specific number of transfer operations is set; data transfer is performed with the transfer
counter stopped (free running mode).
DMCRAH is not used in normal transfer mode. Write 0000h to DMCRAH.
Address(es): DMAC0.DMCRA 0008 2008h, DMAC1.DMCRA 0008 2048h, DMAC2.DMCRA 0008 2088h, DMAC3.DMCRA 0008 20C8h
Normal transfer mode
DMCRAH
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
——————
Value after reset:
0000000000000000
DMCRAL
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Value after reset:
0000000000000000
Repeat transfer mode, block transfer mode
DMCRAH
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
——————
Value after reset:
0000000000000000
DMCRAL
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
000000
Value after reset:
0000000000000000
Symbol Bit Name Description R/W
DMCRAL Lower bits of transfer count Specifies the number of transfer operations R/W
DMCRAH Upper bits of transfer count R/W
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