R01UH0823EJ0100 Rev.1.00 Page 342 of 1823
Jul 31, 2019
RX23W Group 18. DMA Controller (DMACA)
(2) Repeat Transfer Mode (MD[1:0] Bits in DMACm.DMTMD = 01b)
DMCRAH specifies the repeat size and DMCRAL functions as a 10-bit transfer counter.
The number of transfer operations is one when the setting is 001h, 1023 when it is 3FFh, and 1024 when it is 000h. In
repeat transfer mode, a value in the range of 000h to 3FFh (1 to 1024) can be set for DMCRAH and DMCRAL.
Setting bits 15 to 10 in DMCRAL is invalid. Write 0 to these bits.
The value in DMCRAL is decremented by one each time data is transferred until it reaches 000h, at which the value in
DMCRAH is loaded into DMCRAL.
(3) Block Transfer Mode (MD[1:0] Bits in DMACm.DMTMD = 10b)
DMCRAH specifies the block size and DMCRAL functions as a 10-bit block size counter.
The block size is one when the setting is 001h, 1023 when it is 3FFh, and 1024 when it is 000h. In block transfer mode, a
value in the range of 000h to 3FFh can be set for DMCRAH and DMCRAL.
Setting bits 15 to 10 in DMCRAL is invalid. Write 0 to these bits.
The value in DMCRAL is decremented by one each time data is transferred until it reaches 000h, at which the value in
DMCRAH is loaded into DMCRAL.
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