Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 449 of 1823
Jul 31, 2019
RX23W Group 21. I/O Ports
21.4 Initialization of the Port Direction Register (PDR)
Initialize reserved bits in the PDR register according to Table 21.3 and Table 21.4.
 The blank columns in
Table 21.3 and Table 21.4 indicate the bits corresponding to the pins listed in Table 21.1,
Specifications of I/O Ports
.
The corresponding bits should be set to 1 (output) or 0 (input) depending on the user system.
However, the PORT3.PDR.B5 bit of the input-only P35 pin is reserved.
This bit should be set to 0 (input).
 The columns other than the blank columns in
Table 21.3 and Table 21.4 indicate reserved bits.
A reserved bit should be set to 0 (input) or 1 (output) according to
Table 21.3 and Table 21.4.
The B2 and B3 bits of PORT1.PDR, B0 bit of PORT2.PDR, and B2, B3, and B4 bits of PORT3.PDR register are
reserved. Values read from reserved bits are undefined. When writing, read the register and then rewrite the values
that were read to the reserved bit or bits.
When setting a value to a reserved bit, access in byte units.
x: Undefined
x: Undefined
Table 21.3 PDR Register Settings in 85-Pin Packages
Port Symbol
PDR Register
b7 b6 b5 b4 b3 b2 b1 b0
PORT0 1 1 1 1 1
PORT1 × × 1 1
PORT2 1 1 ×
PORT3 0×××
PORT4
PORTB 1 1 1
PORTC 1
PORTD1111 111
PORTE 1 1 1
PORTJ1111 111
Table 21.4 PDR Register Settings in 56-Pin Packages
Port Symbol
PDR Register
b7 b6 b5 b4 b3 b2 b1 b0
PORT011 11111
PORT1 × × 1 1
PORT2 11111×
PORT3 0×××
PORT4 111 1
PORTB 11111
PORTC 1
PORTD1111 111
PORTE111 11
PORTJ11111111

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)