R01UH0823EJ0100 Rev.1.00 Page 1440 of 1823
Jul 31, 2019
RX23W Group 40. SD Host Interface (SDHIa)
Note 3. Set the SDOPT.TOP[3:0] bits to select the number of n cycles.
The SDERSTS2 register indicates the timeout status.
40.2.15 SD Buffer Register (SDBUFR)
The SDBUFR register is used when writing data to the SD card and when reading data from the SD card. The SDBUFR
register is connected to the SDHI’s internal SD buffer. Refer to
section 40.3.1, Data Block Format of the SD Card
for details on the configuration of the SDBUFR register and the SD buffer.
40.2.16 SDIO Mode Control Register (SDIOMD)
Note 1. Do not rewrite this bit when the SDSTS2.CBSY flag is 1.
The SDIOMD register controls reception of the SDIO interrupt, controls CMD52 issuance during multi-block transfer,
and controls the read wait request. Do not set bits C52PUB and IOABT to 1 at the same time.
SDBUFR
Address(es): SDHI.SDBUFR 0008 AC60h
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Value after reset:
Undefined
SDIOMD
Address(es): SDHI.SDIOMD 0008 AC68h
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
— — — — — — — — — — — — — — — —
Value after reset:
0000000000000000
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
— — — — — —
C52PUB IOABT
— — — — —
RWREQ
—
INTEN
Value after reset:
0000000000000000
Bit Symbol Bit Name Description R/W
b0 INTEN
SDIO Interrupt Acceptance
Enable
*1
0: SDIO interrupt accept disabled
1: SDIO interrupt accept enabled
R/W
b1 — Reserved This bit is 0 when read and cannot be modified. R
b2 RWREQ Read Wait Request
0: SDHI exits read wait state
1: Request for SDHI to enter read wait state
R/W
b7 to b3 — Reserved These bits are 0 when read and cannot be modified. R
b8 IOABT SDIO Abort
If this bit is set to 1 during multi-block transfer triggered by CMD53,
CMD52 is immediately issued, and the command sequence is aborted.
R/W
b9 C52PUB SDIO None Abort
If this bit is set to 1 during multi-block transfer triggered by CMD53,
CMD52 is issued before the transfer process is complete, and the
command sequence is completed.
R/W
b31 to b10 — Reserved These bits are 0 when read and cannot be modified. R
To Next Page
Loading...
Need help?
General
