R01UH0823EJ0100 Rev.1.00 Page 142 of 1823
Jul 31, 2019
RX23W Group 6. Resets
6.3 Operation
6.3.1 RES# Pin Reset
This is a reset generated by the RES# pin.
When the RES# pin is driven low, all the processing in progress is aborted and the LSI enters a reset state.
In order to unfailingly reset the LSI, the RES# pin should be held low for the specified power supply stabilization time at
a power-on.
When the RES# pin is driven high from low, the internal reset is canceled after the post-RES# cancellation wait time
(tRESWT) has elapsed, and then the CPU starts the reset exception handling.
For details, see
section 51, Electrical Characteristics.
6.3.2 Power-On Reset and Voltage Monitoring 0 Reset
The power-on reset is an internal reset generated by the power-on reset circuit. A power-on reset is generated when
power is supplied to the RES# pin while it is connected to VCC via a resistor. When connecting a capacitor to the RES#
pin, also ensure that the voltage on the RES# pin is always at least VIH. For details on VIH, refer to
section 51,
Electrical Characteristics
. After VCC has exceeded VPOR and the specified period (power-on reset time) has elapsed,
the internal reset is canceled and the CPU starts the reset exception handling. The power-on reset time is a stabilization
period for the external power supply and the MCU circuit. After a power-on reset has been generated, the PORF flag in
RSTSR0 is set to 1. The PORF flag is initialized by RES# pin reset.
The voltage monitoring 0 reset is an internal reset generated by the voltage monitoring circuit. If the voltage detection
circuit 0 start bit (LVDAS) in option function select register 1 (OFS1) is 0 (voltage monitoring 0 reset is enabled after a
reset) and VCC falls below Vdet0, the RSTSR0.LVD0RF flag becomes 1 and the voltage detection circuit generates
voltage monitoring 0 reset. Clear the OFS1.LVDAS bit to 0 if the voltage monitoring 0 reset is to be used.
Release from the voltage monitoring 0 reset state occurs when VCC rises above Vdet0 and the LVD0 reset time (tLVD0)
elapses, and then the CPU starts the reset exception handling.
Figure 6.1 shows operations during a power-on reset and voltage monitoring 0 reset.
For details on voltage monitoring 0 reset, refer to
section 8, Voltage Detection Circuit (LVDAb).
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