Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1483 of 1823
Jul 31, 2019
RX23W Group 42. Trusted Secure IP (TSIP-Lite)
42.2.2 Encryption Engine
Figure 42.3 shows processes of the encryption engine integrated in the TSIP-Lite.
The encryption engine, using the key generation information, performs plaintext to ciphertext encryption and ciphertext
to plaintext decryption by hardware.
In no part of the encryption or decryption process, is key data or intermediate data ever exposed outside of the TSIP-Lite.
Figure 42.3 Encryption and Decryption processes by Encryption Engine
Key generation information
Encryption
engine
Decryption
Key generation information
Encryption
Plaintext
Ciphertext
Ciphertext
Plaintext
Access
management
circuit
Encryption
engine
Access
management
circuit
TSIP-Lite
TSIP-Lite

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)