Renesas RX Series

R01UH0823EJ0100 Rev.1.00 Page 1641 of 1823
Jul 31, 2019
RX23W Group 47. Comparator B (CMPBa)
47.2.5 Comparator B1 Filter Select Register (CPB1F)
Note 1. The CPBnF[1:0] bits are enabled only when the CPBnFEN bit = 1 (filter is enabled).
47.2.6 Comparator B1 Mode Select Register (CPB1MD)
Note 1. When rewriting the CPB1SPDMD bit, be sure to set the CPBnINI bit (n = 2, 3) in the CPB1CNT1 register to 0 in advance.
Address: 0008 C5A4h
b7 b6 b5 b4 b3 b2 b1 b0
CPB3F[1:0] —
CPB3F
EN
CPB2F[1:0] —
CPB2F
EN
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 CPB2FEN Comparator B2 Filter Enable/Disable
Select*
1
0: Filter is disabled.
1: Filter is enabled.
R/W
b1 — Reserved This bit is read as 0. The write value should be 0. RW
b3, b2 CPB2F[1:0] Comparator B2 Filter Select*
1
b3 b2
0 0: Sampling at PCLK
0 1: Sampling at PCLK/8
1 0: Sampling at PCLK/32
1 1: Sampling at PCLK/64
R/W
b4 CPB3FEN Comparator B3 Filter Enable/Disable
Select*
1
0: Filter is disabled.
1: Filter is enabled.
R/W
b5 — Reserved This bit is read as 0. The write value should be 0. RW
b7, b6 CPB3F[1:0] Comparator B3 Filter Select*
1
b7 b6
0 0: Sampling at PCLK
0 1: Sampling at PCLK/8
1 0: Sampling at PCLK/32
1 1: Sampling at PCLK/64
R/W
Address: 0008 C5A5h
b7 b6 b5 b4 b3 b2 b1 b0
———————
CPB1S
PDMD
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 CPB1SPDMD Comparator B Speed Select 0: High-speed mode
1: Low-speed mode*
1
R/W
b7 to b1 — Reserved These bits are read as 0. The write value should be 0. RW