Renesas RX Series - Serial Sound Interface (SSI); Overview

R01UH0823EJ0100 Rev.1.00 Page 1302 of 1823
Jul 31, 2019
RX23W Group 37. Serial Sound Interface (SSI)
37. Serial Sound Interface (SSI)
This MCU integrates one channel of the serial sound interface (SSI) compliant with the I
2
S bus specification. The SSI
supports I
2
S data format and MSB-first and left-justified/right-justified formats, so it can be used to send or receive audio
data with various devices.
37.1 Overview
Table 37.1 SSI Specifications
Item Specifications
Number of channels One channel (SSI0)
Operating mode Non-compressed mode
Transmission formats
 I
2
S format supported
 MSB-first supported
Left-justified/right-justified formats selectable
Function
 Serves as both a transmitter and a receiver
Channel 0 supports full-duplex communications.
 Capable of various audio formats
 SSISCK0 (serial bit clock) can be selected from among 16, 32, 48, and 64 fs (fs: Sampling rate)
 The master clock (MCLK) can be selected from either of the following:
Master clock pin for audio (AUDIO_MCLK): 1 to 25 MHz
Main clock
 Includes 8-stage FIFO buffers in transmitter and receiver
 Capable of selecting whether to stop word select (SSIWS0) or not when data transmission is stopped
Interrupt sources Three sources
 Communication error
Transmit underflow, transmit overflow, receive underflow, receive overflow, and idle
 Receive data full
 Transmit data empty
Low power consumption
function
Module stop state can be set.