R01UH0823EJ0100 Rev.1.00 Page 1213 of 1823
Jul 31, 2019
RX23W Group 36. CAN Module (RSCAN)
36.2.20 Receive Rule Entry Register jBL (GAFLMLj) (j = 0 to 15)
Modify the GAFLMLj register only when the GRWCR.RPAGE bit is set to 0 in global reset mode.
GAFLIDM[15:0] Bits (ID Mask L)
These bits are used to mask the corresponding ID bit of the receive rule.
Address(es): RSCAN.GAFLML0 000A 83A4h, RSCAN.GAFLML1 000A 83B0h, RSCAN.GAFLML2 000A 83BCh,
RSCAN.GAFLML3 000A 83C8h, RSCAN.GAFLML4 000A 83D4h, RSCAN.GAFLML5 000A 83E0h,
RSCAN.GAFLML6 000A 83ECh, RSCAN.GAFLML7 000A 83F8h, RSCAN.GAFLML8 000A 8404h,
RSCAN.GAFLML9 000A 8410h, RSCAN.GAFLML10 000A 841Ch, RSCAN.GAFLML11 000A 8428h,
RSCAN.GAFLML12 000A 8434h, RSCAN.GAFLML13 000A 8440h, RSCAN.GAFLML14 000A 844Ch,
RSCAN.GAFLML15 000A 8458h
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
GAFLIDM[15:0]
Value after reset:
0000000000000000
Bit Symbol Bit Name Description R/W
b15 to b0 GAFLIDM[15:0] ID Mask L 0: The corresponding ID bit is not compared.
1: The corresponding ID bit is compared.
R/W
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