Renesas RX Series

R01UH0823EJ0100 Rev.1.00 Page 1260 of 1823
Jul 31, 2019
RX23W Group 36. CAN Module (RSCAN)
36.2.79 Global Test Configuration Register (GTSTCFG)
Modify the GTSTCFG register only in global test mode.
RTMPS[2:0] Bits (RAM Test Page Configuration)
These bits are used to set the RAM test target page number for RAM test. Set a value from 00h to 02h.
36.2.80 Global Test Control Register (GTSTCTRL)
RTME Bit (RAM Test Enable)
Setting this bit to 1 enables RAM test. Modify this bit only in global test mode.
(1) Set the GCTRL.GMDC[1:0] bits to 10b (global test mode).
(2) Unlock protection by successively writing 7575h and 8A8Ah to the GLOCKK register
(3) Set the RTME bit to 1.
(4) Check that the RTME bit is set to 1.
Address(es): RSCAN.GTSTCFG 000A 838Ch
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
————— RTMPS[2:0] ————————
Value after reset:
0000000000000000
Bit Symbol Bit Name Description R/W
b7 to b0 — Reserved These bits are read as 0. The write value should be 0. R/W
b10 to b8 RTMPS[2:0] RAM Test Page Configuration Set a value within a range of page 0 (00h) to page 2 (02h). R/W
b15 to b11 — Reserved These bits are read as 0. The write value should be 0. R/W
Address(es): RSCAN.GTSTCTRL 000A 838Eh
b7 b6 b5 b4 b3 b2 b1 b0
—————RTME——
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b1, b0 — Reserved These bits are read as 0. The write value should be 0. R/W
b2 RTME RAM Test Enable 0: RAM test is disabled.
1: RAM test is enabled.
R/W
b7 to b3 — Reserved These bits are read as 0. The write value should be 0. R/W