R01UH0823EJ0100 Rev.1.00 Page 192 of 1823
Jul 31, 2019
RX23W Group 9. Clock Generation Circuit
9.2.19 Memory Wait Cycle Setting Register (MEMWAIT)
Note: Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
Note 1. Do not select the MEMWAIT bit = 0 (no wait states) when divided by 1 is selected by the SCKCR.ICK[3:0] bits and a clock of
frequency is higher than 32 MHz is selected as the system clock (ICLK) by the SCKCR3.CKSEL[2:0] bits. When a clock of
frequency is lower than 32 MHz is selected as the ICLK, it is not necessary to set the MEMWAIT bit to 1 (wait states).
The MEMWAIT register is used to control the wait cycle of the ROM.
MEMWAIT Bit (Memory Wait Cycle Setting)
This bit is used to set the wait cycle of the ROM.
This bit is set to “no wait states” immediately after a reset.
When selecting a clock of frequency higher than 32 MHz as the system clock (ICLK), set the bit to 1 (wait sates).
When setting the MEMWAIT bit to 1 (wait states), make sure that high-speed mode is selected. After the value of the
MEMWAIT bit is changed to 1, change the system clock to a clock of frequency higher than 32 MHz.
When setting the MEMWAIT bit to 0 (no wait states), make sure that the frequency of the system clock (ICLK) is 32
MHz or lower. When changing the operating power control state, make sure that the value of the MEMWAIT bit is
changed to 0.
Table 9.3 lists the restrictions on setting the MEMWAIT bit, and Figure 9.2 and Figure 9.3 show the procedure for
changing the MEMWAIT bit.
Address(es): 0008 0031h
b7 b6 b5 b4 b3 b2 b1 b0
———————
MEMW
AIT
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 MEMWAIT Memory Wait Cycle Setting*
1
0: No wait states
1: Wait states
R/W
b7 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W
Table 9.3 Restrictions on Setting the MEMWAIT Bit
MEMWAIT Bit
Operating Power Control State
High-Speed Operating Mode
Middle-Speed Operating Mode Low-Speed Operating ModeICLK 32 MHz ICLK > 32 MHz
0 Can be set Cannot be set Can be set Can be set
1 Can be set Can be set Cannot be set Cannot be set
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