Renesas RX Series

R01UH0823EJ0100 Rev.1.00 Page 1012 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.2.27 Status Register (STR)
Address(es): SCI12.STR 0008 B327h
b7 b6 b5 b4 b3 b2 b1 b0
— — AEDF BCDF PIBDF CF1MF CF0MF BFDF
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 BFDF Break Field Low Width
Detection Flag
[Setting conditions]
 Detection of the low width for a Break Field
 Completion of the output of the low width for a Break Field
 Underflow of the timer
[Clearing condition]
 Writing 1 to the BFDCL bit in STCR
R
b1 CF0MF Control Field 0 Match
Flag
[Setting condition]
 A match between the value received in Control Field 0 and the set value.
[Clearing condition]
 Writing 1 to the CF0MCL bit in STCR
R
b2 CF1MF Control Field 1 Match
Flag
[Setting condition]
 A match between the data received in Control Field 1 and the set values.
[Clearing condition]
 Writing 1 to the CF1MCL bit in STCR
R
b3 PIBDF Priority Interrupt Bit
Detection Flag
[Setting condition]
 Detection of the priority interrupt bit
[Clearing condition]
 Writing 1 to the PIBDCL bit in STCR
R
b4 BCDF Bus Collision Detected
Flag
[Setting condition]
 Detection of the bus collision
[Clearing condition]
 Writing 1 to the BCDCL bit in STCR
R
b5 AEDF Valid Edge Detection
Flag
[Setting condition]
 Detection of a valid edge
[Clearing condition]
 Writing 1 to the AEDCL bit in STCR
R
b7, b6 — Reserved These bits are read as 0. The write value should be 0. R