R01UH0823EJ0100 Rev.1.00 Page 1205 of 1823
Jul 31, 2019
RX23W Group 36. CAN Module (RSCAN)
DRE Bit (DLC Replacement Enable)
When the DRE bit is set to 1, the DLC value of the receive rule is stored in the buffer instead of the DLC value of the
received message after the DLC value has passed through the DLC filter. In this case, a value of 00h is stored in the data
byte that exceeds the DLC value of the receive rule.
When the DCE bit is set to 1 (DLC check is enabled), the DLC replacement function is available.
MME Bit (Mirror Function Enable)
Setting this bit to 1 makes the mirror function available.
DCS Bit (CAN Clock Source Select)
When this bit is set to 0, the peripheral clock (PCLK) divided by 2 is used as the CAN clock source (fCAN).
When this bit is set to 1, CANMCLK obtained from the EXTAL pin is used as the CAN clock source (fCAN).
TSP[3:0] Bits (Timestamp Clock Source Division)
The clock obtained by dividing the clock source selected by the TSSS bit by the TSP[3:0] value is the count source of the
timestamp counter.
TSSS Bit (Timestamp Clock Source Select)
This bit is used to select a clock source of the timestamp counter.
36.2.10 Global Configuration Register H (GCFGH)
Modify the GCFGH register only in global reset mode.
ITRCP[15:0] Bits (Interval Timer Prescaler Set)
These bits are used to set a clock source division value of the interval timer for FIFO buffers. For details, see
section
36.5.3
(1) Interval Transmission Function.
Address(es): RSCAN.GCFGH 000A 8324h
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
ITRCP[15:0]
Value after reset:
0000000000000000
Bit Symbol Bit Name Description R/W
b15 to b0 ITRCP[15:0] Interval Timer Prescaler Set If the set value is M, PCLK is frequency-divided by M.
Setting 0000h is prohibited when the interval timer is in use.
R/W
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