Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 310 of 1823
Jul 31, 2019
RX23W Group 16. Buses
16.2.6 Parallel Operation
Parallel operation is possible when different bus-master modules are requesting access to different slave modules. For
example, if the CPU is fetching an instruction from ROM and an operand from RAM, the DMAC is able to handle
transfer between a peripheral bus and the peripheral bus at the same time.
An example of parallel operations is shown in
Figure 16.4. In this example, the CPU is able to employ the instruction
and operand buses for simultaneous access to ROM and RAM, respectively. Furthermore, the DMAC simultaneously
employs internal main bus 2 for access to a peripheral bus during access to RAM and ROM by the CPU.
Figure 16.4 Example of Parallel Operations
CPU operand
RAM
ROM
CPU instruction
fetching
DMAC
Peripheral bus Peripheral bus
ROM access
RAM access
Peripheral bus access Peripheral bus access
ROM ROM ROM ROM ROM ROM
RAM RAM RAM RAM RAM RAM

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English