Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 285 of 1823
Jul 31, 2019
RX23W Group 15. Interrupt Controller (ICUb)
15.2.14 NMI Pin Interrupt Control Register (NMICR)
Change the setting of the NMICR register before the NMI pin interrupt is enabled (before setting the NMIER.NMIEN bit
to 1).
NMIMD Bit (NMI Detection Set)
This bit specifies the detection edge of the NMI pin interrupt.
15.2.15 NMI Pin Digital Filter Enable Register (NMIFLTE)
NFLTEN Bit (NMI Digital Filter Enable)
This bit enables the digital filter used for the NMI pin interrupt.
The digital filter is enabled when the NFLTEN bit is 1, and disabled when the NFLTEN bit is 0.
The NMI pin level is sampled at the sampling clock cycle specified with the NMIFLTC.NFCLKSEL[1:0] bits. When the
sampled level matches three times, the output level from the digital filter changes.
For details of the digital filter, see
section 15.4.7, Digital Filter.
Address(es): ICU.NMICR 0008 7583h
b7 b6 b5 b4 b3 b2 b1 b0
————NMIMD———
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b2 to b0 — Reserved These bits are read as 0. The write value should be 0. R/W
b3 NMIMD NMI Detection Set 0: Falling edge
1: Rising edge
R/W
b7 to b4 — Reserved These bits are read as 0. The write value should be 0. R/W
Address(es): ICU.NMIFLTE 0008 7590h
b7 b6 b5 b4 b3 b2 b1 b0
———————
NFLTE
N
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 NFLTEN NMI Digital Filter Enable 0: Digital filter is disabled
1: Digital filter is enabled
R/W
b7 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English