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Renesas RX Series

Renesas RX Series
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R01UH0823EJ0100 Rev.1.00 Page 1216 of 1823
Jul 31, 2019
RX23W Group 36. CAN Module (RSCAN)
36.2.23 Receive Rule Entry Register jCH (GAFLPHj) (j = 0 to 15)
x: Don’t care
Modify the GAFLPHj register only when the GRWCR.RPAGE bit is set to 0 in global reset mode.
GAFLPTR[11:0] Bits (Receive Rule Label)
These bits are used to set a 12-bit label to be attached to messages that have passed through the filter. A label is attached
when a message is stored in the receive buffer or the FIFO buffer.
GAFLDLC[3:0] Bits (Receive Rule DLC)
These bits are used to set the minimum data length necessary for receiving messages. If the data length of a message that
is being filtered is equal to or larger than the value set by the GAFLDLC[3:0] bits, the message passes the DLC check.
Setting these bits to 0000b disables the DLC check function allowing messages with any data length to pass the DLC
check.
Address(es): RSCAN.GAFLPH0 000A 83AAh, RSCAN.GAFLPH1 000A 83B6h, RSCAN.GAFLPH2 000A 83C2h,
RSCAN.GAFLPH3 000A 83CEh, RSCAN.GAFLPH4 000A 83DAh, RSCAN.GAFLPH5 000A 83E6h,
RSCAN.GAFLPH6 000A 83F2h, RSCAN.GAFLPH7 000A 83FEh, RSCAN.GAFLPH8 000A 840Ah,
RSCAN.GAFLPH9 000A 8416h, RSCAN.GAFLPH10 000A 8422h, RSCAN.GAFLPH11 000A 842Eh,
RSCAN.GAFLPH12 000A 843Ah, RSCAN.GAFLPH13 000A 8446h, RSCAN.GAFLPH14 000A 8452h,
RSCAN.GAFLPH15 000A 845Eh
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
GAFLDLC[3:0] GAFLPTR[11:0]
Value after reset:
0000000000000000
Bit Symbol Bit Name Description R/W
b11 to b0 GAFLPTR[11:0] Receive Rule Label Set the 12-bit label information. R/W
b15 to b12 GAFLDLC[3:0] Receive Rule DLC
b15 b12
0000:0 or more data bytes (DLC check is disabled)
0001:1 or more data bytes
0010:2 or more data bytes
0011:3 or more data bytes
0100:4 or more data bytes
0101:5 or more data bytes
0110:6 or more data bytes
0111:7 or more data bytes
1 x x x: 8 or more data bytes
R/W

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