R01UH0823EJ0100 Rev.1.00 Page 245 of 1823
Jul 31, 2019
RX23W Group 11. Low Power Consumption
11.6.3 Software Standby Mode
11.6.3.1 Entry to Software Standby Mode
When a WAIT instruction is executed with the SBYCR.SSBY bit set to 1, a transition to software standby mode is made.
In this mode, the CPU, on-chip peripheral functions, and all the other functions except the sub-clock oscillator stop.
However, the contents of the CPU internal registers, RAM data, the states of on-chip peripheral functions, the I/O ports,
and the sub-clock oscillator are retained. Software standby mode allows significant reduction in power consumption
because the oscillator stops in this mode.
Set the DMAST.DMST bit of the DMAC and the DTCST.DTCST bit of the DTC to 0 before executing the WAIT
instruction.
When the WDT is used, the WDT stops counting when software standby mode is entered.
Counting by the IWDT stops if a transition to software standby mode is made while the IWDT is being used in auto-start
mode and the OFS0.IWDTSLCSTP bit is 1. In the same way, counting by the IWDT stops if a transition to software
standby mode is made while the IWDT is being used in register start mode and the IWDTCSTPR.SLCSTP bit is 1.
Furthermore, counting by the IWDT continues if a transition to software standby mode is made while the IWDT is being
used in auto-start mode and the OFS0.IWDTSLCSTP bit is 0 (counting by the IWDT continues through transitions to
low power consumption modes). In the same way, counting by the IWDT continues if a transition to software standby
mode is made while the IWDT is being used in register start mode and the IWDTCSTPR.SLCSTP bit is 0.
To use software standby mode, make the following settings and then execute a WAIT instruction.
(1) Set the PSW.I bit
*
1
of the CPU to 0.
(2) Set the interrupt request destination
*
2
to be used for recovery from software standby mode to the CPU.
(3) Set the priority
*
3
of the interrupt to be used for recovery from software standby mode to a level higher than the
setting of the PSW.IPL[3:0] bits
*
1
of the CPU.
(4) Set the IERm.IENj bit
*
3
to 1 for the interrupt.
(5) Read the I/O register that is written last and confirm that the written value has been reflected.
(6) Execute a WAIT instruction (executing a WAIT instruction causes automatic setting of the PSW.I bit
*
1
of the CPU
to 1).
Note 1. For details, refer to section 2, CPU.
Note 2. For details, refer to section 15.4.3, Selecting Interrupt Request Destinations.
Note 3. For details, refer to section 15, Interrupt Controller (ICUb).
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