R01UH0823EJ0100 Rev.1.00 Page 847 of 1823
Jul 31, 2019
RX23W Group 31. Independent Watchdog Timer (IWDTa)
31.3.2 Control over Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers
Writing to the IWDTCR, IWDTRCR, or IWDTCSTPR register is only possible once between the release from the reset
state and the first refresh operation.
After a refresh operation (counting starts) or the IWDTCR, IWDTRCR, or IWDTCSTPR register is written to, the
protection signal in the IWDT becomes 1 to protect registers IWDTCR, IWDTRCR, and IWDTCSTPR against
subsequent attempts at writing.
This protection is released by the reset source of the IWDT. With other reset sources, the protection is not released.
Figure 31.5 shows control waveforms produced in response to writing to the IWDTCR register.
Figure 31.5 Control Waveforms Produced in Response to Writing to the IWDTCR Register
3300h
IWDTCR register is protected
(writing-disabled period)
RES# pin
Peripheral module clock
(PCLK)
Data written to IWDTCR
register
IWDTCR register write
signal (internal signal)
IWDTCR register
Register
protection signal
(internal signal)
00F3h
00F3h33F3h (initial value)
Writing disabled
Writing is possible
00F3h 33F3h (initial value)
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